To reduce the number of clocks, the true single-phase clock (TSPC) technique has been advised with the basic registers. Clock network consumes more power consequently, this is necessary to reduce the number of overall clocks. Power consumption in clock distribution network is very significant, which may account 45% of the total system power. Today, in digital integrated circuits, the designing of energy efficient designs is one of the great challenges for the researchers. In CMOS designs, power consumption due to the glitches cannot be ignored as the portion of power consumption varies somewhat between 9% and 38%. Low-power consumption may be obtained efficiently by voltage supply scaling. In memory elements, transient faults may be produced by the preceding combinational circuit glitches. Voltage transient as a result of the collected charge is called a transient fault. The reverse biased electric field produces a drift transient current. When particles touch the drain side of a MOSFET, electron hole combinations are generated. Present studies have shown that device scaling reduces the device capacitances and the supply voltage requirements, and circuit becomes more vulnerable to the glitches. As a result, this is needed to design the flip-flops for lowest power consumption, propagation delay, area, and highest reliability with fault tolerance ability. The performance and fault tolerance ability of the devices are precisely affected by the flip-flops reliability, speed, and power consumption. Today, the flip-flops are widely used for data storage. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system. In the proposed design, we have used an internal dual feedback structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard.